1. Field of the Invention
The present invention relates to systems and methods for protecting printed circuits from reverse engineering and in particular to a system and method for camouflaging a standard cell based integrated circuit.
2. Description of the Related Art
In today's standard-cell based application specific integrated circuit (ASIC) design, the logic function of the chip is modeled and simulated in higher-level hardware description languages (VHDL or VERILOG). It is then synthesized in a silicon compiler (e.g. SYNOPSIS) to generate a netlist using logic cells from a targeted standard-cell library. The netlist will be used in the backend physical design phase to perform the Place and Route of library cells, generating the full circuit layout of the ASIC for manufacturing. The Place and Route process uses an automated computer program placing all logic cells in appropriate locations, then connecting them with metal and via layers according to the connection information in the netlist. ASICs designed using this approach are vulnerable to reverse engineering (RE) attack. RE of an ASIC involves the steps of functional identification of logic cells and the extraction of the cells' connections. With the latest optical and scanning electron microscopic techniques, an ASIC's logic circuits and its wiring network can easily extracted by RE.
In a standard Place and Route process of an ASIC, some unused silicon areas with no logic cells will usually occur during cell placement due to the requirement of efficient routing. The presence of the unused silicon areas provides extra information, like the cell boundaries, to the reverse engineering process. RE usually starts the functional identification of logic cells near the unused silicon areas of the ASIC.
Existing techniques of filling higher metal and via layers to protect the ASIC from RE, described in U.S. Pat. No. 6,924,552, use an algorithm that make the filled layers of metals and vias look like real connectors. This filling technique is not applicable to layers like Metal 1, Contact, Poly and Active layers since these lower layers are not only used as connectors, but are also the basic building layers for P and N MOSFET devices in logic gates.
What is needed is an effective way to fill in the unused silicon spaces of Metal 1, Contact, Poly and Active implants to create a strong camouflage effect to protect the ASIC from reverse engineering.
Another drawback of the technique described in U.S. Pat. No. 6,924,552 is that most of the metals generated are not connected to any voltage source and thus are vulnerable to the ‘voltage contrast’ technique used in reverse engineering. What is also needed is a system and method for connecting a large number of metal wirings generated by the metal fill process of U.S. Pat. No. 6,924,552 to voltage sources.
The present invention satisfies the foregoing needs.